This application is based on and claims the benefit of priority from prior Japanese Patent Application No. 2001-168707, filed on Jun. 4, 2001, the entire content of which is incorporated herein by reference.
1. Field of the Invention
This invention relates generally to semiconductor memory devices and more particularly to redundancy systems for relieving or xe2x80x9crepairingxe2x80x9d defects in memory cells.
2. Description of the Related Art
A redundancy system for use with semiconductor memory chips includes a row redundancy system for repairing defective rows (i.e. rows containing defective cells) and a column redundancy system for repairing defective columns (columns including defective cells), which are typically built together. The row redundancy system is the one that is operatively responsive to input of a row address corresponding to a defective row within a memory array, for providing access to a spare row in lieu of access to such defective row. More specifically, when a row address for selection of a word line containing a defective cell, replacement control is performed in such a way as to activate a spare word line instead of activation of the word line. The column redundancy system is one that is operatively responsive to input of a column address corresponding to a defective column within a memory array while a row corresponding to an input row address within the memory array is accessed (for example, in the state that a word line is activated), for giving access to a spare column in place of access to such defective column. One example is that in a column redundancy system which permits replacement of a column select line (or bit line) with a spare column select line (or spare bit line), replacement control is done for activating a spare column select line (or spare bit line) that performs read/write relative to a spare cell on the accessed row in place of access to such defective column. It is appreciated that the xe2x80x9ccolumn select linexe2x80x9d is not only a signal line for controlling a column switch which connects a selected bit line with a data line, but also a data line in such a column redundancy system that a defective data line is repaired by another data line.
In this way, the currently available redundancy system is not arranged to perform defective cell replacement by replacement with spare cells on a per-cell basis but is arranged generally to replace a plurality of cells aligned in parallel to a defective cell-containing row or column with a plurality of spare cells within a spare row or spare column. In the rest of the description, an aggregation or assemblage of multiple cells in the direction of a row being subjected to defective cell replacement and a signal line for selecting this will be referred to hereinafter as a xe2x80x9cnormal row elementxe2x80x9d or more simply xe2x80x9crow element.xe2x80x9d An assembly of multiple cells in the direction of a column being subject to defective cell replacement and a signal line for selecting this will be called the xe2x80x9cnormal column elementxe2x80x9d or simply xe2x80x9ccolumn elementxe2x80x9d hereinafter. A set of spare cells for use as a defective row/column replacement unit and a signal line for selecting this will be called xe2x80x9credundant element.xe2x80x9d In a system for performing defect replacement relative to both rows and columns, both redundant row elements and redundant column elements are provided. Further, the xe2x80x9celementxe2x80x9d should not be limited only to a set of physically continued cells to be selected by a single signal line and may also be a two-dimensional (2D) aggregation of cells along with a combination or xe2x80x9cbundlexe2x80x9d of multiple signal lines for selecting them together at a time.
See FIG. 18, which shows a redundancy system in one prior known semiconductor memory. A memory array shown herein is subdivided into two, upper and lower memory blocks with a sense-amplifier (S/A) bank interposed therebetween. The lower half memory block includes a redundant row element RELEMENT less than 0 greater than  as disposed therein, which is assigned for replacement of a defective row element found within the lower half memory block. Disposed in the upper half memory block is another redundant row element RELEMENT less than 1 greater than  which is assigned to replacement of a defective row element within the upper half memory block.
The memory array is also bisected laterally into right and left regions as indicated by dotted line in FIG. 18. A redundant column element CELEMENT less than 0 greater than  is disposed in the resultant left half region and is assigned to replacement of a column element within the left half region. Disposed in the right region is a separate redundant column element CELEMENT less than 1 greater than  which is assigned to replacement of a defective column element within the right half region.
In this description, an aggregation of normal elements within the memory array which are replaceable by a certain redundant element will be called the relief or xe2x80x9crepairxe2x80x9d region by means of such redundant element. Repair regions are assigned in units of redundant elements. With the example of FIG. 18, row repair regions assigned to the redundant row elements RELEMENT less than 0 greater than ,  less than 1 greater than  are upper and lower half ones RRA less than 0 greater than ,  less than 1 greater than  of the memory array, respectively; column repair regions assigned to the redundant column elements CELEMENT less than 0 greater than ,  less than 1 greater than  are left and right half ones CRA less than 0 greater than ,  less than 1 greater than  of the memory array, respectively.
A defective cell in the memory array is replaceable by use of either one of a redundant row element or redundant column element. This means that as shown in FIG. 18, a single row repair region must have, without fail, an xe2x80x9coverlap regionxe2x80x9d in which the row repair region at least partially overlaps one or more other column repair regions.
Turning to FIG. 19, there is shown a relationship of redundant row and column regions when looking at a single overlap region. Replacement by means of redundancy is to replace defective elements with redundant elements as described previously. In cases where a defective element includes a cell within this overlap region of interest, part of such defective element as included this overlap region will be called the xe2x80x9cpartialxe2x80x9d defective element. In addition, part of the redundant element for replacement of this partial defective element will be called the partial redundant element. Although in FIG. 19 an exemplary case is shown in which defective cells indicated by markings xe2x80x9cxxe2x80x9d are present in partial defective row and column elements within an overlap region respectively, the defective cells may exist anywhere at defective elements including partial defective elementsxe2x80x94these can be present outside of the overlap region from time to time.
In prior art redundancy systems, the redundant element versus repair region relationship relative to an overlap region is set up so that a redundant row element assigned to a row repair region including such overlap region and a redundant column element assigned to a column repair region including the same overlap region cross or xe2x80x9cintersectxe2x80x9d each other. The mutual intersection of the redundant row and column elements with respect to the overlap region in this way means that a cell on the redundant column element assigned to the same overlap region is selectable by the redundant row element assigned to such overlap region; similarly, any cell on the redundant row element assigned to the overlap region is selectable by the redundant column element assigned to the overlap region.
The feature of prior art redundancy systems may be reworded in a manner such that the relationship of multiple redundant row elements and redundant column elements on a memory chip versus repair regions to which these are assigned is set to satisfy a condition which follows. All available normal row elements for cell selection within an overlap region being subjected to replacement by means of a certain redundant row element (where, the normal row elements include partial normal row elements within the overlap region, or may be completely included in the overlap region, thereby the partial normal row elements being identical to the normal row elements) intersect, without fail, any redundant column element assigned to column replacement within such overlap region. Similarly, all normal column elements for cell selection within an overlap region being presently subject to replacement by means of a certain redundant column element (where, the normal column elements include partial normal column elements within the overlap region, or may be completely included in the overlap region, thereby the partial normal column elements being identical to the normal column elements) intersects with no fail any redundant row element as assigned to row replacement within the overlap region.
Accordingly, in view of the capability to select a cell on a redundant column element by a certain normal row element with respect to a certain overlap region, whenever such normal row element is replaced by a redundant row element, a cell corresponding to the row address of such to-be-replaced normal row element is additionally replaced on the redundant column element also. Similarly, in light of the ability to select a cell on a redundant row element by a certain normal column element with respect to a given overlap region, whenever such normal column element is replaced with a certain redundant column element, a cell corresponding to the column address of such to-be-replaced normal column element is additionally replaced on the redundant row element also.
Additionally, mutual intersection of redundant row and column elements corresponding to an overlap region means that a spare cell is present at a cross point thereof. For example, intersection of a spare word line which is a redundant row element and a spare column select line which is a redundant column element means that a spare cell these lines operate together to select is present. This spare cell is generally known as a xe2x80x9climbo cellxe2x80x9d as shown in FIG. 19. With this system, any cell which resides at the cross-point or intersection of partial row and partial column elements within the overlap region is to be replaced by this limbo cell.
An explanation will be given of problems faced with the prior art redundancy system with reference to FIG. 20 below. As shown in FIG. 20 a semiconductor memory chip is arranged to include a plurality of memory arrays MA less than 0 greater than , MA less than 1 greater than , . . . , MA less than 7 greater than . In the example of FIG. 20, each memory array comes with two redundant row elements RELEMENT and two redundant column elements CELEMENT as disposed therein, wherein two row relief regions and two column relief regions formed thereby are provided. In this way, a great number of redundant row and redundant column elements are present on the memory chip. These redundant row and column elements are combinable in a variety of patterns. However, mutually crossing redundant row and column elements are limited in combinability.
Accordingly, when determining a redundant element assigned to each repair region, designing to permit redundant row and column elements that constitute the so-called overlap region with row and column repair regions overlapping to intersect each other can limit the range of choice of redundant elements while lessening the degree of freedom or flexibility in redundancy designs, which becomes a bar to enhancement of the replacement efficiency or xe2x80x9crepair efficiency.xe2x80x9d In other words, setting a repair region by means of redundant row and column elements in such a way that redundant row/column elements to be assigned to an overlap region have limbo cells such as indicated by xe2x80x9c◯xe2x80x9d in FIG. 20 narrows the range of choice of redundant elements, resulting in limitation of achievement of high repair efficiencies. Additionally, in light of the fact that redundancy circuit designs are closely related to memory array configurations and/or other peripheral circuit designs, the limitation to the flexibility in redundancy designs would result in the entire chip also being limited in design flexibility, which leads to an increase in chip size and/or a decrease in performance.
A semiconductor memory device includes a cell array having a plurality of memory cells, a plurality of first normal elements each defined within said cell array as a group of memory cells arranged in a first direction with a first select line for memory cell selection, a plurality of second normal elements each defined within said cell array as a group of memory cells arranged in a second direction with a second select line for memory cell selection, each said second normal element selecting one or more memory cells in operative association with a corresponding one of said first normal elements, a plurality of first redundant elements disposed for replacement of a defective first normal element within said cell array, and a plurality of second redundant elements disposed for replacement of a defective second normal element within said cell array. In the cell array, first and second repair regions are provided. The first repair region is defined as a group of first normal elements with permission of replacement by each of the first redundant elements. The second repair region is defined as a group of second normal elements with permission of replacement by each of the second redundant elements. At least two of the plurality of first normal elements are activated simultaneously. Whether such simultaneously activated at least two first normal elements are replaced by the first normal elements is controlled independently of each other. At least one of the second redundant elements, which repairs a second normal element having a defect that locates in one of the first repair regions including one of the simultaneously activated at least two first normal elements, does not intersect the one of the simultaneously activated at least two first normal elements.